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ICM7244
Data Sheet January 22, 2009 FN6675.1
8-Character, Microprocessor Compatible, LED Display Decoder Driver
The ICM7244 is an 8-character, alphanumeric display driver and controller which provides all the circuitry required to interface a microprocessor or digital system to a 16-segment display with internal pull-up resistors. It is primarily intended for use in microprocessor systems, where it minimizes hardware and software overhead. Incorporated on-chip are a 64-character ASClI decoder, 8x6 memory, high power character and segment drivers, and the multiplex scan circuitry. 6-bit ASCll data to be displayed is written into the memory directly from the microprocessor data bus. Data location depends upon the selection of either Sequential (MODE = 1) or Random access mode (MODE = 0). In the Sequential Access mode the first entry is stored in the lowest location and displayed in the "left-most" character position. Each subsequent entry is automatically stored in the next higher location and displayed to the immediate "right" of the previous entry. A DISPlay FULL signal is provided after 8 entries; this signal can be used for cascading devices together. A CLR pin is provided to clear the memory and reset the location counter. The Random Access mode allows the processor to select the memory address and display digit for each input word. The character multiplex scan runs whenever data is not being entered. It scans the memory and CHARacter drivers, and ensures that the decoding from memory to display is done in the proper sequence. Intercharacter blanking is provided to avoid display ghosting.
Features
* 6-Segment Fonts with Decimal Point * Has Internal Pull-Up Resistors of 617 Typ. * Mask Programmable for Other Font-Sets Up to 64 Characters * Microprocessor Compatible * Directly Drives LED Common Cathode Displays * Cascadable Without Additional Hardware * Standby Feature Turns Display Off; Puts Chip in Low Power Mode * Sequential Entry or Random Entry of Data Into Display * Single +5V Operation * Character and Segment Drivers, All MUX Scan Circuitry, 8x6 Static Memory and 64-Character ASCll Font Generator Included On-Chip * Pb-Free (RoHS Compliant)
Ordering Information
PART NUMBER (Note) ICM7244AIM44Z ICM7244AIM44ZT PART MARKING ICM7244 AIM44Z ICM7244 AIM44Z TEMP. RANGE (C) -25C to +85C -25C to +85C PACKAGE (Pb-Free) 44 Ld MQFP 44 Ld MQFP (Tape and Reel) PKG. DWG. # Q44.10x10 Q44.10x10
*Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ICM7244 Pinout
ICM7244 (16-SEGMENT CHARACTER) (44 LD MQFP) TOP VIEW
SEG g1 SEG g2 SEG m SEG b SEG c SEG k SEG e SEG f SEG l SEG i VDD
SEG d1 SEG a1 SEG a2 D0 D1 D2 D3 D4 D5 CS NC
1
44 43 42 41 40 39 38 37 36 35 34 33 2 32 3 4 5 6 7 8 9 31 30 29 28 27 26 25 24
SEG d2 DP SEG h SEG j MODE A0/SEN A1/CLR A2/DISP FULL OSC/OFF CHAR1 NC
10
11 23 12 13 14 15 16 17 18 19 20 21 22
VSS
WR
NC
CHAR7
CHAR6
CHAR5
CHAR4
CHAR3
2
CHAR8
CHAR2
NC
FN6675.1 January 22, 2009
ICM7244 Functional Block Diagram
Q DATA INPUT D0 to D5 DATA D LATCHES CL 8x6 6 DATA D0 MEMORY CLR CL ADR D1 17 SEGMENT DRIVERS SEGMENT OUTPUTS SEG x WITH INT PULL-UP RESISTOR OF 617 TYP.
64x17 ROM
WR CS
ONE SHOT
8
CL MODE D
8
8 CHARACTER CHARACTER DRIVERS
CHAR N CHARACTER OUTPUTS
SEL A0/SEN
3 CL D ADDRESS LATCHES
SEL
A1/CLR
MUX
CL D Q CONTROL LATCH
CL EN SEQUENTIAL SEQUENTIAL ADDRESS 3 COUNTER CLR OVERFLOW 3
ADDRESS MULITPLEXER MULTIPLEXER AND DECODER
A2/DISP FULL
OSC/OFF
OSCILLATOR MULTIPLEX OSCILLATOR
CHARACTER MULTIPLEX COUNTER
INTER-CHARACTER BLANKING
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FN6675.1 January 22, 2009
ICM7244
Absolute Maximum Ratings
Supply Voltage VDD - VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V Input Voltage (Any Terminal) . . . . . . . . . . VDD + 0.3V to VSS - 0.3V CHARacter Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . 300mA SEGment Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA
Thermal Information
Thermal Resistance (Typical, Note 1) JA (C/W) MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Maximum Storage Temperature Range . . . . . . . . . .-65C to +150C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-25C to +85C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER DC CHARACTERISTICS Supply Voltage (VDD - VSS) Operating Supply Current Quiescent Supply Current Input High Voltage Input Low Voltage Input Current CHARacter Drive Current CHARacter Leakage Current SEGment Drive Current SEGment Leakage Current DISPlay FULL Output Low DISPlay FULL Output High Display Scan Rate
VDD = 5V, VSS = 0V, TA = +25C, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
VSUPP IDD ISTBY VIH VIL IIN ICHAR ICHLK ISEG ISLK VOL VOH fDS IOL = 1.6mA lIH = 100A VSUPP = 5V, VOUT = 2.5V VSUPP = 5V, VOUT = 1V VSUPP = 5.25V, 10 Segments ON, All 8 Characters VSUPP = 5.25V, OSC/OFF Pin < 0.5V, CS = VSS
4.75 2 -10 140 3.3 2.4 -
5.0 180 30 190 4.5 0.01 400
5.25 250 0.8 +10 100 5.5 10 0.4 -
V mA A V V A mA A mA A V V Hz
Electrical Specifications
PARAMETER AC CHARACTERISTICS WR, CLeaR Pulse Width Low
Drive levels 0.4V and 2.4V, timing measured at 0.8V and 2.0V. VDD = 5V, TA = +25C, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
tWPI tWPH tDH tDS tAH tAS tCS tT tSEN tWDF
300 0 250 125 40 0 0 760
250 250 -100 150 15 -25 540
100 -
ns ns ns ns ns ns ns ns ns ns
WR, CLeaR Pulse Width High (Note 2) Data Hold Time Data Setup Time Address Hold Time Address Setup Time CS Setup Time Pulse Transition Time SEN Setup Time Display Full Delay
Capacitance
PARAMETER Input Capacitance Output Capacitance ClN CO SYMBOL TEST CONDITIONS (Note 3) (Note 3) MIN TYP 5 5 MAX UNITS pF pF
2. In Sequential mode WR high must be TSEN +TWDF . 3. For design reference only, not tested.
4
FN6675.1 January 22, 2009
ICM7244 Timing Waveforms
CS tCS
tAH tAS ADDRESS VALID tWPI WRITE tDS tT DATA VALID tT tDH tWC tWHP
FIGURE 1. RANDOM ACCESS TIMING
CHAR 1 tSEN CLEAR CHAR 2 CHAR 8
WR
tWPH
SEN tWDF DISPLAY FULL
FIGURE 2. SEQUENTIAL ACCESS MODE TIMING (MODE = 1)
~5s
INTERNAL INTER-CHARACTER BLANKING SIGNAL CHAR 1
~300s
CHAR 2
CHAR 3
CHARACTERS DRIVE SIGNALS
CHAR 4
CHAR 5 INTER-CHARACTER BLANKING
CHAR 6
CHAR 7
CHAR 8
FIGURE 3. DISPLAY CHARACTERS MULTIPLEX TIMING DIAGRAM
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FN6675.1 January 22, 2009
ICM7244 Pin Descriptions
SIGNAL D0 - D5 CS WR MODE PIN 4 thru 9 10 13 29 6-Bit ASCll Data input pins (active high). Chip Select from P address decoder, etc. WRite pulse input pin (active low). For an active high write pulse, CS can be used. Selects data entry MODE. High selects Sequential Access (SA) mode where first entry is displayed in "leftmost" character and subsequent entries appear to the "right". Low selects the Random Access (RA) mode where data is displayed on the character addressed via A0 thru A2 Address pins. In RA mode it is the LSB of the character Address. In SA mode it is used for cascading devices for displays of more than 8 characters (active high enables device controller). In RA mode this is the second bit of the address. In SA mode, a low input will CLeaR the Serial Address Counter, the Data Memory and the display. In RA mode this is the MSB of the Address. In SA mode, the output goes high after 8 entries, indicating DISPlay FULL. OSCillator input pin. Adding capacitance to VDD will lower the internal oscillator frequency. An external oscillator can be applied to this pin. A low at this input sets the device into a (shutdown) mode, shutting OFF the display and oscillator but retaining data stored in memory. SEGment driver outputs. FUNCTION
A0/SEN A1/CLR A2/DISP FULL OSC/OFF
28 27 26 25
SEG d1, SEG a1, SEG a2, SEG j, SEG h, DP, SEG d2, SEG f, SEG i, SEG b, SEG g2, SEG I, SEG m, SEG e, SEG g1, SEG k, SEG c CHAR8 thru CHAR5, CHAR4 thru CHAR2, CHAR1
1 thru 3, 30 thru 38 40 thru 44
14 thru 17, 19 thru 21, 24
CHARacter driver outputs.
6
FN6675.1 January 22, 2009
ICM7244 Test Circuit
17 SEGMENTS
CHAR 8 CHAR 7 CHAR 6 CHAR 5 CHAR 4 CHAR 3 CHAR 2 CHAR 1
SEGMENTS SEG g1 SEG g2 SEG m SEG b SEG c SEG k SEG e SEG f SEG l SEG i
SEG d1 SEGMENTS SEG a1 SEG a2 D0 VDD D1 D2 D3 D4 D5 CS NC
VDD
1
44 43 42 41 40 39 38 37 36 35 34 33 2 32 3 4 5 6 7 8 9 31 30 29 28 27 26 25 24
SEG d2 DP SEG h SEG j MODE (SA/RA) A0/SEN A1/CLR A2/DISP FULL OSC/OFF CHAR1 NC DISPLAY FULL OUTPUT VDD NC (FOR SA MODE) VDD SEGMENTS
10
11 23 12 13 14 15 16 17 18 19 20 21 22
CHAR5 VSS
WR
NC
CHAR8
CHAR7
CHAR6
CHAR4
CHAR3
FIGURE 4.
7
CHAR2
NC
FN6675.1 January 22, 2009
ICM7244 Typical Applications
8 CHARACTERS 8 CHARACTERS
+5V CHAR RRI RBR8 RBR7 HD6402 UART CLR CS ICM7244 SEN WR D0 - D5 CS DISP FULL SEN WR D0 - D5 CS CLR CS ICM7244 SEG CHAR SEG
DISP FULL ETC.
RBR1 - RBR6 DRR DR
6 BIT BUS
+5V +5V 20k OUT V+ SEN TR ICL7555 DELAY TH 200pF CLR CHAR SEG ICM7244 DISP FULL CS D0 - D5 CS WR
+5V D0 - D5 CS SEN ICM7244 CLR CHAR SEG DISP FULL ETC. CS WR
8 CHARACTERS
8 CHARACTERS
FIGURE 5. DRIVING TWO ROWS OF CHARACTERS FROM A SERIAL INPUT
8
FN6675.1 January 22, 2009
ICM7244 Typical Applications
(Continued)
8-CHARACTER LED DISPLAY 8-CHARACTER LED DISPLAY
8-CHARACTER LED DISPLAY
8
NOTE
8
NOTE
8
NOTE
CLR
CLR
CHAR SEG
CLR
CHAR SEG
CLR
CHAR SEG
+5V +5V
SEN MODE WR D0 - D5
DISP FULL VDD VSS +5V +5V
CS
SEN MODE WR D0 - D5
DISP FULL VDD VSS +5V +5V
CS
SEN MODE WR D0 - D5
DISP FULL VDD VSS +5V
CS
DATA BUS WR CS, (WR)
6
6
6
FIRST 8 CHARACTERS
SECOND 8 CHARACTERS
NTH 8 CHARACTERS
NOTE: 17 for ICM7244. FIGURE 6. MULTICHARACTER DISPLAY USING SEQUENTIAL ACCESS MODE
+5V
+5V
+5V
+5V 1k
+5V 1.4APEAK 2N6034
617 1mA 2N2219 SEG
617
SEG 300 1k ICM7244 25 r ON = 4 CHAR (100mAPEAK) 2N2219
ICM7244
14 (100mAPEAK)
CHAR r ON = 4
14mA 2N6034 1.4APEAK GND GND 1k GND
GND
GND
FIGURE 7A. COMMON CATHODE DISPLAY
FIGURE 7B. COMMON ANODE DISPLAY
FIGURE 7. DRIVING LARGE DISPLAYS
9
FN6675.1 January 22, 2009
ICM7244 Typical Applications
(Continued)
8 CHARACTERS 8 CHARACTERS 8 CHARACTERS 8 CHARACTERS
ICM7244 CS A2 A1 A0 D0 - D5 WR P22 P21 80C35 80C48 P20
ICM7244 CS A2 A1 A0 D0 - D5 WR
ICM7244 CS A2 A1 A0 D0 - D5 WR
ICM7244 CS A2 A1 A0 D0 - D5 WR
DB7 DB6 DB5 - DB0 WR 6 BIT BUS
FIGURE 8. RANDOM ACCESS 32-CHARACTER DISPLAY IN A 80C48 SYSTEM
Display Font and Segment Assignments
a1 f h g1 e m d2 0 0 l i a2 j g2 k d1 c DP b
0
1
D5, D4
1
0
1
1
D3 D2 D1 D0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
FIGURE 9. 16-SEGMENT CHARACTER FONT WITH DECIMAL POINT
10
FN6675.1 January 22, 2009
ICM7244 Display Font and Segment Assignments
VDD SEGMENT DRIVER VLED = 1.6V RTYPICAL = 617
(Continued)
R
SEG x
DISPLAY
CHARACTER DRIVER CHAR N rDS(ON) ~ 4m VSS SEGMENT LEDs
FIGURE 10. SEGMENT AND CHARACTER DRIVERS OUTPUT CIRCUIT
Detailed Description
WR, CS
These pins are immediately functionally ANDed, so all actions described as occurring on an edge of WR, with CS enabled, will occur on the equivalent (last) enabling or (first) disabling edge of any of these inputs. The delays from CS pins are slightly (about 5ns) greater than from WR due to the additional inverter required on the former.
Address Counter. If this output is low, and SEN is (latched) high, the contents of the Counter will be used to establish the Data Memory location for the Data input. The Counter is then incremented on the rising edge of WR. If SEN is low, or DISPlay FULL is high, no action will occur. This allows easy "daisy-chaining" of display drivers for multiple character displays in a Sequential Access mode.
Changing Modes
Care must be exercised in any application involving changing from one mode to another. The change will occur only on a falling edge of WR (or its equivalent). When changing mode from Sequential Access to Random Access, note that A2/DlSPlay FULL will be an output until WR has fallen low, and an Address drive here could cause a conflict. When changing from Random Access to Sequential Access, A1/CLR should be high to avoid inadvertent clearing of the Data Memory and Sequential Address Counter. DISPlay FULL will become active immediately after the rising edge of WR.
MODE
The MODE pin input is latched on the falling edge of WR (or its equivalent, see WR description). The location (in Data Memory) where incoming data will be placed is determined either from the Address pins or the Sequential Address Counter. This is controlled by MODE input. MODE also controls the function of A0/SEN, A1/CLR, and A2/DlSPlay FULL lines.
Random Access Mode
When the internal mode latch is set for Random Access (RA) (MODE latched low), the Address input on A0, A1 and A2 will be latched by the falling edge of WR (or its equivalent). Subsequent changes on the Address lines will not affect device operation. This allows use of a multiplexed 6-bit bus controlling both address and data, with timing controlled by WR.
Data Entry
The input Data is latched on the rising edge of WR (or its equivalent) and then stored in the Data Memory location determined as described above. The six Data bits can be multiplexed with the Address information on the same lines in Random Access mode. Timing is controlled by the WR input.
Sequential Access Mode
If the internal latch is set for Sequential Access (SA), (MODE latched high), the Serial ENable input or SEN will be latched on the falling edge of WR (or its equivalent). The CLR input is asynchronous, and will force-clear the Sequential Address Counter to address 000 (CHARacter 1), and set all Data Memory contents to 100000 (blank) at any time. The DISPlay FULL output will be active in SA mode to indicate the overflow status of the Sequential
OSC/OFF
The device includes a relaxation oscillator with an internal capacitor and a nominal frequency of 200kHz. By adding external capacitance to VDD at the OSC/OFF pin, this frequency can be reduced as far as desired. Alternatively, an external signal can be injected on this pin. The oscillator (or external) frequency is pre-divided by 64, and then further divided by 8 in the Multiplex Counter, to drive the
11
FN6675.1 January 22, 2009
ICM7244
CHARacter drive lines ( Figure 3). An inter-character blanking signal is derived from the pre-divider. An additional comparator on the OSC/OFF input detects a level lower than the relaxation oscillator's range, and blanks the display, disables the DISPlay FULL output (if active), and clears the pre-divider and Multiplex Counter. This puts the circuit in a low-power-dissipation mode in which all outputs are effectively open circuits, except for parasitic diodes to the supply lines. Thus a display connected to the output may be driven by another circuit (including another ICM7244) without driver conflicts. the CHARacter outputs, except during the inter-character blanking interval (nominally about 5s). Each CHARacter output lasts nominally about 300s, and is repeated nominally every 2.5ms, i.e., at a 400Hz rate (times are based on internal oscillator without external capacitor). The 6 bits read from the Data Memory are decoded in the ROM to the 17 segment signals, which drive the SEGment outputs. Both CHARacter and SEGment outputs are disabled during WR operations (with SEN high and DISPlay FULL Low for Sequential Access mode). The outputs may also be disabled by pulling OSC/OFF low. The decode pattern from 6 bits to 17 segments is done by a ROM pattern according to the ASCll font shown. Custom decode patterns can be arranged, within these limitations, by consultation with the factory.
Display Output
The output of the Multiplex Counter is decoded and multiplexed into the address input of the Data Memory, except during WR operations (in Sequential Access mode, with SEN high and DISPlay FULL low), when it scans through the display data. The address decoder also drives
12
FN6675.1 January 22, 2009
ICM7244 Metric Plastic Quad Flatpack Packages (MQFP)
D D1 -D-
Q44.10x10 (JEDEC MS-022AB ISSUE B) 44 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE
INCHES SYMBOL A A1 MIN 0.004 0.077 0.012 0.012 0.515 0.389 0.516 0.390 0.029 44 0.032 BSC MAX 0.096 0.010 0.083 0.018 0.016 0.524 0.399 0.523 0.398 0.040 MILLIMETERS MIN 0.10 1.95 0.30 0.30 13.08 9.88 13.10 9.90 0.73 44 0.80 BSC MAX 2.45 0.25 2.10 0.45 0.40 13.32 10.12 13.30 10.10 1.03 NOTES 6 3 4, 5 3 4, 5 7 Rev. 2 4/99 NOTES:
0.076 0.003
-AE E1
-B-
A2 b b1 D D1 E
e
PIN 1 SEATING PLANE
E1 L N e
-H-
A
12o-16o 0.40 0.016 MIN 0o MIN 0o-7o A2 A1 0.20 M 0.008 C A-B S
-CDS b b1 0.13/0.17 0.005/0.007 BASE METAL WITH PLATING 0.13/0.23 0.005/0.009
1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. All dimensions and tolerances per ANSI Y14.5M-1982. 3. Dimensions D and E to be determined at seating plane -C- . 4. Dimensions D1 and E1 to be determined at datum plane -H- . 5. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm (0.010 inch) per side. 6. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total. 7. "N" is the number of terminal positions.
L
12o-16o
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 13
FN6675.1 January 22, 2009

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